Principal PCIe CXL RTL Design Engineer, Aix-en-Provence
Principal PCIe CXL RTL Design Engineer, Aix-en-Provence
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Aix-en-Provence, France
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Publiée: il y a moins d’un mois
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Description
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe and CXL standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.
Rambus offers a flexible work environment, embracing a hybrid approach. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Benefits include an excellent health insurance, Employee Stock Purchase Plan, an extra day of vacation per quarter, regular team lunches and breakfasts and a great team atmosphere.
Responsibilities
Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP
Implement these designs in System Verilog
Collaborate with the verification team to verify the IPs
Participate in prototyping of the IPs in cutting edge FPGAs
Qualifications
RTL coding: Verilog / System Verilog
Master's degree or PhD in Electrical Engineering, Computer Engineering or equivalent.
5+ years of experience with RTL Design
Good English skills, communication skills, and willingness to work with an international team.
Additional Desirable Skills
Knowledge of PCIe / CXL
Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.
Rambus is proud to be an Equal Employment Opportunity and Affinitive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.
Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.
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This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe and CXL standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.
Rambus offers a flexible work environment, embracing a hybrid approach. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Benefits include an excellent health insurance, Employee Stock Purchase Plan, an extra day of vacation per quarter, regular team lunches and breakfasts and a great team atmosphere.
Responsibilities
Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP
Implement these designs in System Verilog
Collaborate with the verification team to verify the IPs
Participate in prototyping of the IPs in cutting edge FPGAs
Qualifications
RTL coding: Verilog / System Verilog
Master's degree or PhD in Electrical Engineering, Computer Engineering or equivalent.
5+ years of experience with RTL Design
Good English skills, communication skills, and willingness to work with an international team.
Additional Desirable Skills
Knowledge of PCIe / CXL
Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.
Rambus is proud to be an Equal Employment Opportunity and Affinitive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.
Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.
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Informations clefs
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Nom de l’entrepriseRambus.com
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Titre de postePrincipal PCIe CXL RTL Design Engineer
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Principal PCIe CXL RTL Design Engineer est visible sur Locanto dans la catégorie Aix-en-Provence Design, Conception.
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