Co-design engineer for future computing architectures in …, Saclay
Co-design engineer for future computing architectures in …, Saclay
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Saclay, France
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Dernière édition le: il y a moins d’une semaine
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Description
Co-design engineer for future computing architectures in HPC– M/F Contrat: CDD (fixed-term contract)
Cadre: 24
Site: Saclay
Expiration date: 08/06/2026
We are looking for a co-design engineer for future computing architectures in HPC. This position, in a fixed-term contract, is based at the Nano-Innov site of Paris-Saclay, Essonne (91).
As part of a multidisciplinary team specializing in hardware IP design and EDA tools, you will develop innovative methodologies and tools for HW/SW co-design of electronic architectures, focusing on high-performance computing (HPC) and AI systems.
You will leverage VPSim (virtual prototyping) and A-DECA (architecture exploration)—tools that enable HW modeling, binary SW execution, functional validation, and performance analysis in a fully virtualized environment. These tools integrate QEMU-based emulation, external models, and a Python API for performance data extraction during application execution. A-DECA further supports efficient design space exploration via optimization strategies.
This role is part of EU-funded research projects on next-gen HPC networks and open-source EDA tools, with a focus on optical/photonic interconnects to address latency, bandwidth, and scalability challenges in large-scale computing.
Responsibilities
Understand the technical specifications of the computing system integrating an optical link and develop the appropriate model in the VPSim platform;
Develop a high-level virtual prototype based on the CEA VPSIM simulation tool to provide first estimations of KPIs and allow system-of-chiplets architecture exploration;
Determine the best architectural parameters in terms of power, performance, area and sustainability using the A-DECA tool;
Collaborate and communicate with other research partners involved to expand the CEA VPSIM tool to model optical-switch based architectures;
Assume responsibility to assess, prepare, and contribute software components to open-source ecosystems;
Participate in the scientific dissemination of the team's research results (contributions to publications in national and international conferences), design of videos, demonstrations, and tutorials as well as in the valorization of the innovations.
Qualifications
Engineering or master's degree, or PhD in computer science, electronics or embedded systems.
Knowledge of digital electronic architecture (processors, caches, NoC, etc.).
High level programming language skills: C++, Java, Scala, etc.
Scripting languages: Bash, Python, etc.
Familiarity with development tools: IDE, make/cmake, SVN/Git, continuous integration, Docker.
Experience in simulation/emulation, especially with QEMU.
Experience in other scripting languages (Bash, TCL) is a plus.
Knowledge in the field of operational research and/or machine learning algorithms is a plus.
In accordance with the commitments made by the CEA to promote the integration of disabled people, this job is open to all. The CEA proposes arrangements and/or organizational possibilities for the inclusion of disabled workers.
Reference: 2026-39914
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Cadre: 24
Site: Saclay
Expiration date: 08/06/2026
We are looking for a co-design engineer for future computing architectures in HPC. This position, in a fixed-term contract, is based at the Nano-Innov site of Paris-Saclay, Essonne (91).
As part of a multidisciplinary team specializing in hardware IP design and EDA tools, you will develop innovative methodologies and tools for HW/SW co-design of electronic architectures, focusing on high-performance computing (HPC) and AI systems.
You will leverage VPSim (virtual prototyping) and A-DECA (architecture exploration)—tools that enable HW modeling, binary SW execution, functional validation, and performance analysis in a fully virtualized environment. These tools integrate QEMU-based emulation, external models, and a Python API for performance data extraction during application execution. A-DECA further supports efficient design space exploration via optimization strategies.
This role is part of EU-funded research projects on next-gen HPC networks and open-source EDA tools, with a focus on optical/photonic interconnects to address latency, bandwidth, and scalability challenges in large-scale computing.
Responsibilities
Understand the technical specifications of the computing system integrating an optical link and develop the appropriate model in the VPSim platform;
Develop a high-level virtual prototype based on the CEA VPSIM simulation tool to provide first estimations of KPIs and allow system-of-chiplets architecture exploration;
Determine the best architectural parameters in terms of power, performance, area and sustainability using the A-DECA tool;
Collaborate and communicate with other research partners involved to expand the CEA VPSIM tool to model optical-switch based architectures;
Assume responsibility to assess, prepare, and contribute software components to open-source ecosystems;
Participate in the scientific dissemination of the team's research results (contributions to publications in national and international conferences), design of videos, demonstrations, and tutorials as well as in the valorization of the innovations.
Qualifications
Engineering or master's degree, or PhD in computer science, electronics or embedded systems.
Knowledge of digital electronic architecture (processors, caches, NoC, etc.).
High level programming language skills: C++, Java, Scala, etc.
Scripting languages: Bash, Python, etc.
Familiarity with development tools: IDE, make/cmake, SVN/Git, continuous integration, Docker.
Experience in simulation/emulation, especially with QEMU.
Experience in other scripting languages (Bash, TCL) is a plus.
Knowledge in the field of operational research and/or machine learning algorithms is a plus.
In accordance with the commitments made by the CEA to promote the integration of disabled people, this job is open to all. The CEA proposes arrangements and/or organizational possibilities for the inclusion of disabled workers.
Reference: 2026-39914
#J-18808-Ljbffr
Informations clefs
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Nom de l’entrepriseCEA
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Titre de posteCo-design engineer for future computing architectures in HPC - M/F
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