Lead Tech– Analog and Mixed-Signal (AMS) IC Design …, Grenoble

Lead Tech– Analog and Mixed-Signal (AMS) IC Design Lead Tech is the guardian of the technical architecture and performance of integrated circuits (ICs). They drive technological choices and oversee the entire implementation process, from initial specifications to GDSII (tape‑out). They ensure design robustness against Process, Voltage, and Temperature (PVT) variations in a specific cryotemperature environment. He is also responsible for managing the team, subcontractors, and service providers.

Technical Challenges

Architecture&Specification:

Define the architecture for critical blocks (ADC/DAC, PLL, PMU, filters, amplifiers, Mux, control…) and translate system requirements into circuit‑level specifications.

Design&Simulation:

Supervise transistor‑level design, corner simulations, noise analysis, and mismatch analysis. A specific point of our designs is the very low operating temperature (100 mK to 4 K).

Layout Guidance:

Lead layout engineers on matching issues, parasitic coupling, and signal integrity.

Mixed‑Signal Verification (AMS):

Define verification plans for operation at the interface between the analog and digital domains.

Post‑Silicon Validation:

Collaborate with test teams to characterize chips in the lab and analyze measurements and tests.

R&D&Innovation:

Evaluate new architecture and operating temperature partitioning and protect innovations through patent filing.

Technical Expertise&Skills Scientific Expertise:

Semiconductor Physics, Block Design, Signal Integrity&ESD, Modeling (Verilog‑A, MATLAB), Architecture study.

EDA Tools (CAD):

Cadence Virtuoso, Simulators (Eldo), Physical Verification (Calibre LVS/DRC), Parasitic Extraction (PEX).

Soft Skills:

Extreme scientific rigor, technical decision‑making, managing junior engineers, foundry and subcontractor communication skills.

Design Reviews:

Organize and approve critical milestones prior to fabrication (tape‑out).

Risk Management:

Identify potential failure points regarding performance, yield and long‑term reliability.

Foundry and subcontractor Interface:

Act as the primary technical point of contact for foundries, partners and subcontractors.

Methodology:

Improve internal design flows to increase efficiency and simulation accuracy.

Management:

Managing a junior team.

Key Performance Indicators (KPIs)

First‑Pass Success:

Ability to achieve functional silicon on the first revision.

Performance vs. Specs.

Tape‑out Deadline Compliance:

Deliver the final design on‑time vs the roadmap.

Documentation Quality:

Simulation reports and integration manuals.

Candidate Profile

Education:

Master’s Degree in Microelectronics or PhD in a related field.

Experience:

8 to 12 years of minimum experience. Several successful tape‑outs are mandatory.

A unique workplace, combining industrial dynamism, technological innovation and a unique natural and cultural living environment.

The opportunity to continue to train, to develop skills by working with the best researchers in the field.

A collaborative work environment, a culture that has trust as its pillar and where your work will be recognized, and much more!

Contribute to the influence of Quobly through the sharing of our progress in international conferences.

The possibility of having a pro‑life balance with a standard day package of 213 days worked/year.

The possibility of teleworking up to 4 days a week depending on the position.

Offices near Grenoble train station or Paris downtown.

Assistance with soft travel or public transport.

We are an equal opportunity employer and welcome applications from all qualified individuals.

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