Staff Hardware Design Engineer, La Ciotat

About SiFive: As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications. SiFive’s compute platforms enable leading technology companies worldwide to innovate, optimize, and deliver advanced solutions across agriculture, automotive, data center, mobile, and consumer markets.Job Description

SiFive is seeking a Senior Hardware Design Engineer specialized in IOMMU (Input-Output Memory Management Unit) and Virtualization architectures. The engineer will lead the development of our MSI Translation Engine (MTE), a specialized component that leverages IOMMU-like mechanisms for Message Signaled Interrupt translation. This role bridges core MMU design and system‑level interconnects and utilizes our Chisel‑based hardware generation framework to build highly configurable IP that scales from embedded systems to server‑class SoCs.Responsibilities

Own the microarchitecture of the MSI Translation Engine, ensuring strict latency and throughput targets for high‑performance computing and automotive applications. Develop RTL generators using Chisel (Scala) with an emphasis on modularity and extreme configurability. Design and optimize the MTE’s internal memory hierarchy, including TLBs, MSHRs, and local metadata caches.Collaborate with Core MMU and Architecture teams to align MTE behavior with the RISC‑V AIA (Advanced Interrupt Architecture) and H‑extension specifications. Partner with DV teams to create rigorous test plans for complex corner cases, such as page faults during interrupt translation. Work with Physical Design to ensure timing closure on advanced process nodes.Position Requirements

7+ years of industry experience in RTL design, focusing on memory management, interrupt controllers, or complex SoC IP. Proven expertise with memory systems: TLB design, MSHRs, cache controllers. Strong understanding of IOMMU mechanisms, two‑stage address translation, and hypervisor‑level memory isolation.Experience with the RISC‑V LTI protocol is a plus. Familiarity with PCIe stack, including ATS and PRI, and their interaction with system‑level translation engines. Expert‑level knowledge of AMBA protocols, specifically AXI4. Proficiency in an OO or functional language such as Scala, C++, or Java; experience with Chisel/Scala highly preferred.Advanced proficiency in SystemVerilog or Verilog with a focus on high‑quality, maintainable code. Fluency in English and the ability to document complex microarchitectural specifications clearly. MS/PhD in Electrical Engineering, Computer Engineering, or a related technical discipline. Additional Information

This position requires successful background and reference checks and proof of right to work in France. Any offer of employment is contingent on verification of authorized access to export‑controlled technology under applicable export control laws or successful procurement of required licenses or approvals.SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

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