Principal Hardware Architect, Nice
Principal Hardware Architect, Nice
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Nice, France
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Dernière édition le: il y a moins d’un mois
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Description
Our client is a leading global player in the development of SoCs used in the automotive, AI, mobile, edge computing, data center, and aerospace industries. The company develops highly configurable IPs and software integration tools for complex systems subject to stringent performance, scalability, and reliability requirements.
Position Context You will play a key role in defining, optimizing, and evolving cache coherency solutions within an advanced IP portfolio.
Your primary mission will be to design next-generation architectures to ensure efficient and coherent communication between processors, accelerators, and functional units.
You will work closely with hardware design, verification, and software development teams, as well as with product and sales teams, to deliver high-performance, low-power, and highly reliable NoC solutions.
Key Responsibilities
Design complete, scalable, and robust cache coherency architectures and ensure seamless integration into the overall system architecture
Optimize architecture and micro-architecture to reduce latency and increase bandwidth
Define performance, power, and area (PPA) targets; identify performance bottlenecks and power consumption issues
Evaluate chiplet partitioning through die-to-die and chip-to-chip architectures based on standards such as CHI C2C, UAlink, UCIe, and PCIe
Provide technical expertise to Application Engineering teams to facilitate product integration at customer sites
Interact with marketing and sales teams to gather customer needs and market requirements
Collaborate closely with hardware design, software, and system architecture teams
Maintain active technology watch on cache coherency advancements; evaluate new standards, methodologies, and industry trends
Produce detailed technical documentation: architecture specifications, design guides, white papers
Profile Sought Required Qualifications
Engineering degree, Master’s degree, or equivalent in microelectronics, computer science, or a related field
Proven experience as a Cache Coherency Architect, SoC/NoC Architect, or senior SoC design engineer
Why This Position Is Attractive
Cutting-edge, complex SoC/NoC environment closely aligned with industry evolution
Direct impact on technical decision-making
Strong cross-functional exposure and direct interaction with international teams: hardware, software, Application Engineering, marketing, and sales
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Position Context You will play a key role in defining, optimizing, and evolving cache coherency solutions within an advanced IP portfolio.
Your primary mission will be to design next-generation architectures to ensure efficient and coherent communication between processors, accelerators, and functional units.
You will work closely with hardware design, verification, and software development teams, as well as with product and sales teams, to deliver high-performance, low-power, and highly reliable NoC solutions.
Key Responsibilities
Design complete, scalable, and robust cache coherency architectures and ensure seamless integration into the overall system architecture
Optimize architecture and micro-architecture to reduce latency and increase bandwidth
Define performance, power, and area (PPA) targets; identify performance bottlenecks and power consumption issues
Evaluate chiplet partitioning through die-to-die and chip-to-chip architectures based on standards such as CHI C2C, UAlink, UCIe, and PCIe
Provide technical expertise to Application Engineering teams to facilitate product integration at customer sites
Interact with marketing and sales teams to gather customer needs and market requirements
Collaborate closely with hardware design, software, and system architecture teams
Maintain active technology watch on cache coherency advancements; evaluate new standards, methodologies, and industry trends
Produce detailed technical documentation: architecture specifications, design guides, white papers
Profile Sought Required Qualifications
Engineering degree, Master’s degree, or equivalent in microelectronics, computer science, or a related field
Proven experience as a Cache Coherency Architect, SoC/NoC Architect, or senior SoC design engineer
Why This Position Is Attractive
Cutting-edge, complex SoC/NoC environment closely aligned with industry evolution
Direct impact on technical decision-making
Strong cross-functional exposure and direct interaction with international teams: hardware, software, Application Engineering, marketing, and sales
#J-18808-Ljbffr
Informations clefs
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Nom de l’entrepriseBREAM&LAANAIA
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Titre de postePrincipal Hardware Architect
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