Senior Physical Design Engineer, Rennes

Our client is a major player in the semiconductor industry, specializing in the design of embedded microcontrollers and microprocessors for AI applications and complex chip architectures.

We are looking for a Physical Design Engineer to join a team responsible for the back-end design of 32-bit MCUs and microprocessors.

The role will include:

Implement all aspects of physical design, such as floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance, and physical verification.

Perform all aspects of Chip Power Integrity for multiple voltage domains, such as IR drop analysis, signal EM, and Power EM

Utilize hierarchical systems‑level design techniques to build designs exceeding multi‑million gates.

Work on the place and route methodologies and low power methodologies.

Must be a self‑motivated team player who can collaborate with multiple teams across a geographically diverse company to achieve desired design goals.

Autonomy and leadership opportunities

Detailed job functions include:

Timing closure support to maximize process node capability.

Clock tree setup/debug and synthesis for optimal QoR.

General physical implementation procedures.

Multi‑voltage island‑based floorplan design and support.

Flow development and automation implementation.

Die size estimation and bond out approval.

Interfacing with external vendors and IP sources to resolve problems.

Working with members from international design/implementation teams.

Requirements/Qualifications: The successful candidate will have a minimum of 10+ years or more applicable technical experience in the physical and timing‑related aspects of IC design. The design task requires experience in the following Physical Design‑related activities:

Advanced knowledge of VLSI logic principles, power integrity and reliability (EM&IR) analysis.

Advanced knowledge of place and route methodologies and low power methodologies.

Knowledge of clock tree synthesis&debug, and design timing closure.

Experience with 40nm technologies and beyond is required.

Detailed systems‑level floorplanning.

Power network planning.

Multi‑voltage/low power implementation techniques.

Detailed knowledge of Innovus or ICC/ICC2, and Redhawk toolsets.

Proficiency in Tcl, Python and Perl scripting is essential.

Excellent debugging and analytical skills.

Good verbal and written communication skills and strong interpersonal skill

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